Various systems controlled by recent computers or microprocessors require the development of an electrically erasable and programmable read-only memory (hereinafter referred to as a EEPROM) of a high density. Particularly, since the use of a hard disk with a rotary magnetic disk as a secondary storage occupies a relatively large area in a portable computer system such as a battery-powered computer system of notebook size, system designers take much interest in the development of EEPROMs of high density and high performance occupying a smaller area. To achieve a high density EEPROM, it is a major problem to reduce the area occupied by memory cells. To solve such a problem, an EEPROM has been developed which contains NAND structured cells being capable of decreasing the number of selection transistors per cell and contact holes coupled with a bit line. Such a NAND structured cell is disclosed in the IEDM, pp 412 to 415, 1988 under the title of "NEW DEVICE TECHNOLOGIES FOR 5 V-ONLY 4 Mb EEPROM WITH NAND STRUCTURE CELL". This NAND structured cell (hereinafter referred to as a NAND cell unit or a NAND cell) is comprised of a first selection transistor whose drain is connected to the corresponding bit line via a contact hole; a second selection transistor whose source is connected to a common source line; and eight memory transistors whose channels are connected in series between the source of the first selection transistor and the drain of the second selection transistor. The NAND cell is formed on a p-type semiconductor substrate, and each memory transistor includes a floating gate layer formed on a gate oxide layer over a channel region between its source and drain regions and a control gate layer separated from the floating gate layer by an intermediate insulating layer. To program of write a selected memory transistor in the NAND cell, operation of simultaneously erasing all memory transistors therein must be followed by the programming operation. The simultaneous erasure is performed by applying 0 volts to the bit line and rasing the gate of the first selection transistor and control gates of all memory transistors to 17 volts. This causes all memory transistors to be changed into enhancement mode transistors which are assumed as binary logic "1" programmed transistors. To program a selected memory transistor to a binary logic "0", 22 volts are applied to the bit line, the gate of the first selection transistor and control gates of memory transistors between the first selection transistor and the selected memory transistor, while 0 volts are applied to the control gate of the selected memory transistor, control gates of memory transistor between the selected memory transistor and the common source line, and the gate of the second selection transistor. Thus, the selected memory transistor is changed into a depletion mode transistor by the Fowler-Nordheim tunneling (F-N tunneling) of holes from its drain to its floating gate. However, the problem of programming in this manner is that a portion of the gate oxide of the selected memory transistor is subjected to a stress induced by application of the high voltage to its drain, and the partially stressed gate oxide causes leakage current to flow. This results in degrading more and more the data retention capability of the memory cell according to an increase of the number of cycles of erasing and/or programming, thereby reducing the reliability of the EEPROM. To solve this problem, an improved device structure, in which the NAND cells are formed on a p-type well region imbedded in an n-type semiconductor substrate, and further improved erasing and programming technologies utilizing the improved device structure are disclosed in the symposium on VLSI Technology, pp 129 to 130, 1990 under the title of "A NAND STRUCTURED CELL WITH A NEW PROGRAMMING TECHNOLOGY FOR HIGHLY RELIABLE 5 V-ONLY FLASH EEPROM".
Erasure of all memory transistors in this NAND cell is performed by applying 0 volts to all control gates and a high potential of 20 volts to the p-type well region and the n-type substrate, thereby uniformly extracting electrons from their floating gates to the well region. As a result, each memory transistor has a threshold voltage of about -4 volts which represents a state of depletion mode, i.e. a logic "0". To program a selected memory transistor in the NAND cell, a high voltage of 20 volts is applied to the gate of the first selection transistor and the control gate of the selected memory transistor, while 0 volts are applied to the gate of the second selection transistor, and an intermediate voltage of 7 volts is applied to control gates of unselected memory transistors. If the selected memory transistor is to be written or programmed into a logic "1", 0 volts are applied to the bit line connected with the NAND cell, thereby injecting electrons into the floating gate of the selected memory transistor. This results in causing the selected memory transistor to become enhancement mode. On the contrary, if the selected memory transistor is to be programmed to a logic "0", a program inhibition voltage of 7 volts instead of 0 volt is applied to the bit line to inhibit the programming of the selected memory transistor. Since such a programming operation uniformly injects electrons from the p-type well to its floating gate via its gate oxide layer, the partial stress on the thin gate oxide layer does not occur to a significant degree, and the gate oxide leakage current may thus be prevented.
However, when the memory capacity becomes high, such ways of uniform erasing and programming cause problems in the case that system designers want to erase a portion or a block of previously written or programmed memory cells in order to reprogram. In this case, a conventional approach is to simultaneously erase all memory transistors in a memory cell array, i.e. to carry out a flash erasure, and then to newly reprogram the content of all programs. Thus, since significantly reusable portions or blocks of the memory array are simultaneously erased, the reprogramming not only needs a long time, but also is inconvenient. It may be appreciated that such problems seriously occur when the memory density becomes more higher. To solve these problems, it is made possible only to erase all memory transistors in a selected memory block. However, in the case of an EEPROM using the above-mentioned improved erasing and programming techniques, to prevent the erasing of all memory transistors in an unselected block, it is required that a high voltage equal to an erase voltage or a high voltage of about 18 volts or more be placed on their control gates. Thus, this technology has a drawback that a decoding circuit for performing a block erasing operation becomes complicated on design. In addition, when the density of the EEPROM cells increases, an on-chip occupying area of the decoder increases, thereby making it difficult to design the decoder.
Another problem for the prior art is that of programming. To prevent the programming of non-programmed memory transistors, which must maintain previous data, of memory transistors on a selected word line, it is required that each of bit lines corresponding to the non-programmed memory transistors be raised to the intermediate, i.e. the program inhibiting voltage, via a charge pump circuit connected thereto. In addition, when the memory capacity is increased, the number of bit lines or the length of each bit line is increased. Consequently, it is necessary that a high voltage generating circuit on the same chip for supplying the high voltages to the charge pump circuits has a high performance. Such a high voltage generating circuit and the charge pump circuits give a problem in increasing the area occupied by the on-chip peripheral circuits.
Conventional EEPROMs include a page program mode for high-speed programming. The page programming operation is composed of a data loading operation and a programming operation. The data loading operation comprises sequentially latching or storing data of a byte size from input/output terminals to a data register. The programming operation comprises simultaneously writing the data stored in the data register into memory transistors on a selected word line via bit lines. The page programming technology on an EEPROM with NAND cells is disclosed in the IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 25, NO. 2, pp 417 to 423, APRIL 1990.
Conventional EEPROMs employ a programming verification technique to enhance their reliability. The verification means checking to determine if programmed cells are programmed so as to have desired threshold voltages. Technologies of the programming verification may be classified into an external verification technique controlled by a microprocessor and an internal verification technique performed by an on-chip verification circuit. The external verification technique is disclosed in the IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 26, NO. 4, pp 492 to 495, April 1991 and U.S. Pat. No. 5,053,990. The external verification technique has a problem in that it takes a predetermined long time to determine if programmed cells are well programmed. In addition, whenever reprogramming is performed after the failure of the programming, it is necessary that the data loading operation is performed again. However, the internal verifying technique has an advantage that the programming verification is performed at a higher speed. The internal verifying technique is disclosed in Korean Patent Laid Open NO. 91-17445 and U.S. Pat. No. 4,811,294. In these documents, the verification is performed in such a manner that comparator means compare data stored in a data register with data read out in pages from memory cells via sense amplifiers. However, such a scheme employing comparator means increases an occupied area of on-chip peripheral circuits.